1. Field of the Invention
Generally, the present disclosure relates to the fabrication of integrated circuits, and, more particularly, to the formation of metallization layers and contaminations related thereto in subsequent processes.
2. Description of the Related Art
Semiconductor devices are typically formed on substantially disc-shaped substrates made of any appropriate material. The majority of semiconductor devices including highly complex electronic circuits are currently, and in the foreseeable future will be, manufactured on the basis of silicon, thereby rendering silicon substrates and silicon-containing substrates, such as silicon-on-insulator (SOI) substrates, viable carriers for forming semiconductor devices, such as microprocessors, SRAMs, ASICs (application specific ICs) and the like. The individual integrated circuits are arranged in an array form, wherein most of the manufacturing steps, which may add up to 500-1000 or more individual process steps in sophisticated integrated circuits, are performed simultaneously for all chip areas on the substrate, except for photolithography processes, certain metrology processes and packaging of the individual devices after dicing the substrate. Thus, economical constraints drive semiconductor manufacturers to steadily increase the substrate dimensions, thereby also increasing the area available for producing actual semiconductor devices.
In addition to increasing the substrate area, it is also important to optimize the utilization of the substrate area for a given substrate size so as to actually use as much substrate area as possible for semiconductor devices and/or test structures that may be used for process control. In the attempt to maximize the useful surface area for a given substrate size, the peripheral chips are positioned as closely to the substrate perimeter as is compatible with substrate handling processes. Generally, most of the manufacturing processes are performed in an automated manner, wherein the substrate handling is performed at the back side of the substrate and/or the substrate edge, which typically includes a bevel at least at the front side of the substrate.
Due to the ongoing demand for shrinking the feature sizes of highly sophisticated semiconductor devices, copper and alloys thereof, in combination with a low-k dielectric material, have become a frequently used alternative in the formation of so-called metallization layers, which include metal lines and vias connecting individual circuit elements to provide the required functionality of the integrated circuit. Although copper exhibits significant advantages when compared to aluminum being the typical metallization metal for the last decade, semiconductor manufacturers have been somewhat reluctant to introduce copper in the production owing to copper's ability to readily diffuse in silicon and silicon dioxide. Moreover, even when being present in very small amounts, copper may significantly modify the electrical characteristics of silicon and, thus, the behavior of circuit elements, such as transistors and the like. It is, therefore, essential to confine the copper to the metal lines and vias by using appropriate insulating and conductive barrier layers so as to strongly suppress the diffusion of copper into sensitive device regions. Furthermore, any contamination of process tools, such as transport means, transport containers, robot arms, wafer chucks and the like, must be effectively restricted, since even minute amounts of copper deposited on the back side of a substrate may lead to diffusion of the copper into sensitive device areas.
The problem of copper and other device and tool contamination is even exacerbated when low-k dielectric materials are employed in combination with copper to form metallization layers, owing to the reduced mechanical stability of the low-k dielectrics. Since at least some of the deposition processes used in fabricating semiconductors may not be efficiently restricted to the “active” substrate area, a stack of layers or material residues may also be formed at the substrate edge region including the bevel, thereby generating a mechanically unstable layer stack owing to process non-uniformities at the substrate edge and especially at the bevel of the substrate. In particular, low-k dielectrics formed by chemical vapor deposition (CVD) tend to adhere more intensively at the bevel edge region compared to the active substrate region, thereby building up an increased layer thickness that may be up to twice the thickness of the dielectric material in the active region. Thus, during the formation of a plurality of metallization layers, a layer stack at the bevel region may be formed that includes barrier material, copper and dielectrics, which exhibit a reduced adhesion to each other. During the further production and substrate handling processes, material such as copper, barrier material and/or the dielectrics may delaminate and significantly affect these processes, thereby negatively affecting production yield and tool integrity.
For instance, in forming a copper-based metallization layer, the so-called inlaid or damascene technique is presently a preferred manufacturing method to create metal lines and vias. To this end, a dielectric layer, typically comprised of a low-k dielectric, is deposited and patterned to include trenches and vias in accordance with design requirements. During the patterning process, polymer materials, which may be used for adjusting the etch characteristics of the patterning process, may be deposited on substrate areas of highly non-uniform process conditions, such as the substrate edge, the bevel and the adjacent back side area. The polymer materials, which include fluorine, may additionally contribute to modified adhesion properties for any other material that may be deposited in subsequent processes, thereby contributing to an increased tendency for causing delamination events. Therefore, in some approaches, a respective wet chemical clean process may be performed in an attempt to remove the polymer residuals. Thereafter, a conductive barrier layer comprised of, for example, tantalum, tantalum nitride, titanium, titanium nitride and the like, may be deposited, wherein the composition of the barrier layer is selected so as to also improve the adhesion of the copper to the neighboring dielectric. The deposition of the barrier layer may be accomplished by CVD or physical vapor deposition (PVD), wherein a deposition of the barrier material may not be efficiently restricted to the active substrate area by presently established deposition techniques. Consequently, the barrier material may also be deposited at the substrate bevel and partially at the back side of the substrate, thereby forming, in combination with residues of the dielectric material that may not be efficiently removed by the previous etch processes for patterning the dielectric layer, a layer stack of reduced mechanical stability, wherein any polymer residuals that may have not been removed efficiently due to a limited efficiency of the previous wet clean process may additionally reduce the mechanical stability. Thereafter, according to a standard damascene process flow, a thin copper seed layer is deposited by PVD or similar appropriate processes to initiate and promote a subsequent electrochemical deposition process to fill the trenches and vias formed in the dielectric material.
Although reactor vessels for the electrochemical deposition, such as electroplating reactors or electroless plating reactors, may be designed such that substantially no copper is deposited at the substrate edge, the preceding seed layer deposition process may nevertheless result in a significant deposition of unwanted copper at the substrate edge region. After the electrochemical deposition of the bulk copper, any excess material has to be removed. This is frequently achieved by chemical mechanical polishing (CMP), wherein material fragments, such as copper pieces, may “flake off” owing to the reduced stability of the metallization layer stack, especially at the substrate bevel. The copper-containing material flakes and other material flakes comprised of dielectric material and/or barrier material, for instance liberated during the CMP process, may then re-deposit at unwanted substrate regions or may affect the CMP process of subsequent substrates. During the further processing of the substrate, a contamination, mainly caused by the delamination at the substrate edge, may occur and may especially adversely affect the so-called back end process flow, in which contact pads and solder bumps are formed.
Since contamination caused by, for instance, unwanted copper at the substrate edge has been identified as a major contamination source, great efforts are being made to remove copper from the substrate edge and the bevel substantially without affecting the inner, i.e., the active, substrate region. To this end, etch modules have been developed by semiconductor equipment providers, such as Semitool Inc., Novellus Inc. and the like, which are configured to selectively provide an agent substantially comprised of sulfuric acid and hydrogen peroxide to the substrate edge so as to remove unwanted copper from this region. Although the removal of unwanted copper from the substrate edge reduces the risk of copper contamination of subsequent processes, it turns out, however, that a significant reduction of production yield, especially in the manufacturing sequence for higher metallization layers and in the back end process flow, is still observable.
The present disclosure is directed to various methods that may solve, or at least reduce, some or all of the aforementioned problems.